Flash EPROM is differentiated from EPROM by the fact that Flash devices can be programmed and erased up to a guaranteed multiple number of times, whereas EPROM can only be programmed one time. In typical operation of Flash EPROM, programming, or writing, of the memory array is done on a byte-by-byte (or bit-by-bit) basis; in contrast, erasing (or resetting) of the memory array is done on a global (whole block) basis. Various sophisticated in-circuit algorithms are typically employed by Flash manufacturers to ensure that the Flash memory array can be reliably programmed and erased for a high number of erase cycles (typically&gt;100,000 cycles). It has been found that the number of achievable program/erase cycles is directly correlated to the threshold voltage distribution of the erased bits. In other words, the greater the disparity in threshold voltages between cells, the fewer the number of available program/erase cycles. This is due to the fact that over-erased bits can cause difficulty in subsequent re-programming of the memory array, and this results in failure of the entire device. In addition, over-erased bits can potentially have high enough leakage current to cause a false reading when sensing of data is done on neighboring bits sharing the same bit line, even if these neighboring bits are at high V.sub.t. Therefore, efforts in the field of Flash programming research have focused on tightening the V.sub.t distribution of the memory array after erase operation.
In most of the prior art, to facilitate a tight erase V.sub.t distribution, all the memory cells are first programmed before commencing an erase operation. This programming operation, commonly known as "pre-programming", is performed to ensure that all the cells are at a uniformly high V.sub.t before they are then globally erased. This pre-program operation can be thought of as a pre-conditioning of the array prior to erase operation. The theory underlying this approach is based on an assumption that if pre-programming is not done before an erase operation, then cells with stored electrons or data will be at a high V.sub.t, while cells without stored electrons or data will be at a low V.sub.t at the beginning of the erase operation. This relatively wide V.sub.t distribution at the beginning of an erase operation will translate into a wide erased V.sub.t distribution at the end of the same operation. If instead all the cells are placed at a uniformly high V.sub.t prior to an erase operation, the occurrence of some of the bits having over-erasure problems is minimized. Thus the benefits of pre-programming are well-understood in the art, including the fact that it results in enhancement of the overall reliability of a Flash memory array.
To effectuate a pre-programming (conditioning) operation, the prior art typically uses the same mechanism as used in a normal array programming operation. Currently, the most preferred method for programming, and thus for pre-programming, is the use of Channel Hot Electron Injection, or CHEI. This method typically takes about 3-10 .mu.s per bit, with each bit consuming about a peak current of 300 .mu.A. The operation typically is done one byte, or 8 bits, at a time, until a whole sector is pre-programmed.
Unfortunately, the use of CHEI for pre-programming can exacerbate another degradation mechanism of flash cells. In particular, CHEI involves the use of high energy (hot) electrons. These hot electrons, along with the hot holes they generate in the channel of the device, can severely degrade the trans-conductance (known as Gm), and thus limit the current handling capability of the Flash memory cell. As is to be expected, this effect is more pronounced as the channel length of the Flash cell is progressively scaled downward. As currently understood, the Gm degradation mechanism is irreversible. A Flash memory cell with a severely degraded Gm will yield significantly reduced current during reading, and this results in yet another failure mechanism for the memory array.
In addition, the CHEI mechanism tends to saturate at a high threshold voltage, on the order of the control gate voltage (V.sub.pp) of the cell. Thus, even if a pre-programming operation is performed to ostensibly set threshold voltages at a value of V.sub.tp, the threshold voltage distribution at end of such pre-programming can nevertheless have a range between V.sub.tp and V.sub.pp. In some common applications, this distribution can still be as wide as 3 volts, which is excessive and can lead to further mis-operation of the device.
Yet another drawback of using CHEI for pre-programming is that as the supply voltage for the technology is scaled down below 3V, it takes progressively longer to perform the pre-program operation (and thus an erase operation as well). This is because the CHEI mechanism is not easily scalable with supply voltage. During a CHEI pre-programming operation, the drain of the cell being pre-programmed must be charge pumped to a higher voltage than the source voltage; typically this difference is in excess of 4.5 volts. Consequently, instead of being capable of performing pre-program of 8 bits simultaneously, the pre-program operation might need to be done with less than 4 bits at a time. This in effect doubles the time required for pre-programming. Furthermore as cell sizes are scaled down, a large amount of current is consumed in supply the charge pump, making this prior art method even less efficient. To compensate against this effect, the charge pump must be made larger in order to supply the same amount of current for a reduced voltage. This trend would only get worse as the supply voltage is further scaled to 1.8V and below, and the die size increases.
It can be seen therefore that the goal of decreasing the charge pump size (to scale it proportionately in accordance with the memory cell array) is not realized easily in practice because to do so defeats the goal of keeping (or certainly improving) the pre-program (erase) times. Thus, to maintain the same erase speeds, a proportionately larger (relative to the cell size) charge pump is required, and this results in overall reduced device integration density, higher fabrication costs, etc.
Accordingly, there is a substantial need for a pre-programming mechanism that does not significantly degrade device performance, and that provides a tighter V.sub.t distribution after a pre-programming operation. In addition, it is extremely desirable for such pre-programming method to be easily scalable with the supply voltage of flash devices.